Power dissipation in CMOS circuits exponentially increases with technology scaling. It is required to reduce both dynamic and leakage power by means of analysis carried out at various level of abstraction. In this paper, DWT architecture based on lifting scheme is considered and dynamic power reduction is achieved by suitable modification of the architecture. The interdependency of scaling and dilation coefficients is simplified to single hierarchy, which reduces latency and increases throughput. Wallace tree multiplier and carry select adder are used in realizing this 1D-DWT architecture that operates at a maximum frequency of 280 MHz. Power consumption of the multiplier is optimized by voltage scaling technique. The 1D-DWT architecture is modified and its performances are analyzed. Simulation results shows that the dynamic power consumption is reduced by 37%. The proposed design is implemented using 65 nm TSMC low power library cells and is synthesized using Synopsys DC

Keywords: Dynamic power dissipation, DWT, Lifting Scheme, Adders, Multipliers