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TITLE : FIN-FET TECHNOLOGY FOR ULTRA LOW POWER DESIGN  
AUTHORS : Shivani Kothari                 
DOI : http://dx.doi.org/10.18000/ijies.30119  
ABSTRACT :

In this paper we first explore the sub-threshold conduction and region. Our analysis indicate that the energy consumption is very less in Fin-FET than CMOS technology in sub-threshold region. In the paper it is also concluded that by using pull down network the power consumption can be reduced further. By using Fin-FET domino logic the technology is scaled down to the 33nm and delay in the circuit is also reduced.

 
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