FPGAs are less power-efficient than custom ASICs. So in this paper we reviewed some latest research work on power reduction in FPGA at 90nm, 45nm and 28nm CMOS technology node, we examined that using dual VT and fine-grained VDD techniques static power reduces to 64% and 95 % respectively. While using LOPASS, glitch reduction and clock gating techniques dynamic power reduces to 61.6%, 30%, and 50% respectively. We also discussed about novel non-classical ultra-low power MOS devices like Multi-Gate FET and Tunneling FET which we can use in FPGAs to yield low power with high performance and high speed.