Today leakage power has become an increasingly major issue in low power VLSI design. With the most important element of leakage, the sub-threshold current, exponentially increasing with decreasing device dimension, leakage commands associate ever increasing share in the processor power consumption. In this paper two techniques such as transistor stacking and self controllable voltage-level (SVL) circuit for reducing leakage power in sequential circuits are proposed. This work analysis the power and delay of three different types of D Flip-flops using pass transistors logic, transmission gates and gate diffusion input (GDI) cmos design style. All the circuit parameters are simulated with and without the application of leakage reduction techniques. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameters