In response to meet higher routing complexity in System - On - Chip (SoC), Network - On - Chip (NoC) has been proposed as a flexible and scalable solution. Router design is one of the most important factors that significantly impacts NoC system performance. Therefore, acquiring an accurate estimation of the router performance is an important parameter in Networks-on-Chip. In this paper, optimum router model is designed for NoC and explains how it can be used to study the effect of changing the queue size, routing algorithm and the number of ports. Queuing Analysis is used to obtain an analytical model for an NoC based router for mesh topology with reduced overall delay and power consumption.